1. Field
Exemplary embodiments of the present invention relate to a power voltage selection device for selecting one of a plurality of power voltages.
2. Description of the Related Art
As an electronic technology has been developed, sizes of electronic devices have been minimized. Thus, electronic devices including a laptop computer, a mobile communication device and the like are requested to operate with power voltages having various voltage levels that are supplied from various power voltage suppliers located at various places. Moreover, if a plurality of power voltages is supplied to the electronic devices, the electronic devices are requested to select one of the plurality of power voltages, and supply a selected power voltage stably irrespective of characteristics of the selected power voltage.
For example, portable electronic devices are designed to operate with various power voltages supplied from an alternating current (AC) power adapter or a battery. If the AC power adapter is coupled to the portable electronic devices, a power voltage is supplied from the AC power adapter to the portable electronic devices. If the AC power adapter is not coupled to the portable electronic devices, a power voltage is supplied from the battery included in the portable electronic devices to the portable electronic devices.
In other words, if the external power voltage is supplied to the electronic devices, the electronic devices operate with the external power voltage, and if an external power voltage is not supplied to the electronic devices, the electronic devices operate with an internal power voltage. These electronic devices are thus requested to select one of a plurality of power voltages.
FIG. 1 is a circuit diagram illustrating a conventional power voltage selection device.
Referring to FIG. 1, a conventional power voltage selection device includes a power voltage selection unit 10 and an output unit 20.
The power voltage selection unit 10 includes a first PMOS transistor P11 and a second PMOS transistor P12.
A first enable signal EN_1 is input to a gate of the first PMOS transistor P11. A source and a body of the first PMOS transistor P11 are coupled to each other. A first power voltage VDD1 is coupled to the source of the first PMOS transistor P11. A second enable signal EN_2 is input to a gate of the second PMOS transistor P12. A source and a body of the second PMOS transistor P12 are coupled to each other. A second power voltage VDD2 is coupled to the source of the second PMOS transistor P12. A drain of the first PMOS transistor P11 is coupled to a drain of the second PMOS transistor
The output unit 20 includes an output node VOUT, and supplies a selected power voltage to an external device (not shown) through the output node VOUT. The drain of the first PMOS transistor P11 and the drain of the second PMOS transistor are commonly coupled to the output node VOUT.
An operation of the conventional power voltage selection device will be described as below.
In operation, the first power voltage VDD1 is output to the output node VOUT in response to the first enable signal EN_1 that is input to the gate of the first PMOS transistor P11. Alternatively, the second power voltage VDD2 is output to the output node in response to the second enable signal EN_2 that is input to the gate of the second PMOS transistor P12.
More specifically, if the first enable signal EN_1 having a low voltage level of a ground voltage or a negative voltage is input to the gate of the first PMOS transistor P11, the first PMOS transistor P11 is turned on in response to the first enable signal EN_1, and the first power voltage VDD1 is output to the output node VOUT. If the second enable signal EN_2 having a low voltage level of a ground voltage or a negative voltage is input to the gate of the second PNOS transistor P12, the second PNOS transistor P12 is turned on in response to the second enable signal EN_2, and the second power voltage VDD2 is output to the output node VOUT. Since the first enable signal EN_1 and the second enable signal EN_2 do not have a low voltage level at the same time, the first PMOS transistor P11 and the second transistor P12 are not turned on at the same time.
FIG. 2 is a cross sectional view of a conventional PMOS transistor.
As shown in FIG. 2, a PMOS transistor includes a drain coupling terminal 11_1 a gate coupling terminal 11_2, a source coupling terminal 11_3 an oxide layer 11_4, a P-type doped substrate 11_5, an N-type doped well 11_6, a P-type doped drain 11_7 and a P-type doped source 11_8.
The PMOS transistor also includes a first parasitic diode 11_A, a second parasitic diode 11_B and a third parasitic diode 11_C. The N-type doped well 11_6 is diffused in the P-type doped substrate 11_5. The first parasitic diode 11_A is formed along a boundary between the N-type doped well 11_6 and the P-type doped substrate 11_5.
The P-type doped drain 11_7 and the P-type doped source 11_8 are diffused in the N-type doped well 11_6. The second parasitic diode 11_B is formed between the P-type doped drain 11_7 and the N-type doped drain well 11_6, and the third parasitic diode 11_C is formed between the p-type doped source 11_8 and the N-type doped well 11_6.
The first parasitic diode 11_A and the second parasitic diode 11_B form a parasitic bipolar junction transistor (BJT). The first parasitic diode 11_1 and the third parasitic diode 11_C form a parasitic BJT.
Referring to FIGS. 1 and 2, if a delay occurs in a power-up sequence of the first power voltage VDD1 and the second power voltage VDD2, a latch-up occurs in the PMOS transistor of the conventional power voltage selection device. The latch-up is defined as a phenomenon that a parasitic transistor is turned on and an unwanted current flows due to a mutually amplified operation.
For example, if the second power voltage VDD2 is supplied to the source of the second PMOS transistor P12 while the first power voltage VDD1 is not supplied to the source of the first PMOS transistor P11, and the source of the first PMOS transistor P11 has a ground voltage, the body of the first PMOS transistor P11 coupled to the first power voltage VDD1 has a ground voltage, and the second power voltage VDD2 is supplied to the drain of the first PMOS transistor P11.
If a voltage difference between the body and the drain of the first PMOS transistor P11 is higher than a threshold voltage, the parasitic transistor is turned on and the latch-up occurs.
As described above, in a conventional system, a large amount of current is input to an integrated circuit due to the latch-up caused by the parasitic transistor, which may increase a power consumption of a semiconductor device and heat the semiconductor device.